Package Board Co-Simulation Using Equivalent Circuit Modeling Method for High-Speed System

Abstract

This research paper focuses on the challenges of system-level simulations for high-speed data transfer and the importance of modeling methodology in achieving accurate results. The simulating of PCB alone without considering the package model is not enough. Instead, to ensure optimal system performance, simulating the packages and PCBs together is essential. When simulating the high-speed parallel bus at the PCB level, it's crucial to consider the package model. If the package model is missing, achieving successful results can be challenging. In this paper, a method is proposed for developing a package model that is specific to the nets required for simulation purposes. The paper explores the challenge of simulating high-speed interfaces with a DDRx example that includes an RLC package model. An interconnect model technique is developed to apply the package RLC model through the equivalent circuit modeling method for the high-speed DDRx test board. This solution aims to simplify the co-design process by using simulation and verifying the model with the assistance of an eye diagram of the data bus. The proposed package model reduces jitter in co-simulation and ensures timing compliance for high-speed interfaces.