Suppression of Simultaneous Switching Noise Using Embedded Capacitor Method in High-Speed Systems

Abstract

Gbps signals are commonly used in modern high-speed IO designs. These systems require a high level of signal accuracy. However, these signals can cause current fluctuations at high frequencies due to parasitic inductance on the package and board, leading to significant changes in supply voltage. DDRX interfaces that transmit data up to 4.8 Gbps induce simultaneous switching noise (SSN) in the voltage regulator module (VRM). One of the adverse effects of SSN is timing jitter, also known as power supply-induced jitter. The amount of SSN is directly proportional to the number of signals on a parallel bus. Discrete capacitors may not be effective in reducing SSN impact when data is transmitted at high speeds. The current approach used to predict and evaluate errors in SSNs relies on the designer's expertise, which requires accurate estimates of packaging parasitic. In this paper, a practical approach to lessen SSN is presented through the use of embedded capacitors placed between planes and optimizing discrete capacitors by connecting them in a way that measures the impact of supply noise on the I/O transistor circuit performance at the DDRX interface. Two boards were designed, evaluated, and subsequently compared their results.